Forum Discussion
fxu001
Occasional Contributor
Occasional Contributortiming in I/O pads
Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi Fred,
Do you have any other questions or help needed?
Thanks.
-YY
fxu001Occasional Contributor
Occasional ContributorHi YY,
I am pretty smooth to debug this FPGA so far. I only have one question: do you know or ever hear that Altera FPGA can increase sensitivity for the LVDS input pin beside board to change terminator or layout trace width or length. I already turn on LVDS terminator. I ask this question because one of bit_clock signals is too weak that cause miss detect data frequently. Besides, I am fine now.
Thanks,
-Fred
