timing in I/O pads

Hi YY, I am pretty smooth to debug this FPGA so far. I only have one question: do you know or ever hear that Altera FPGA can increase sensitivity for the LVDS input pin beside board to change terminator or layout trace width or length. I already turn on LVDS terminator. I ask this question because one of bit_clock signals is too weak that cause miss detect data frequently. Besides, I am fine now. Thanks, -Fred

Hi YY, Oh, I think I might change design architecture to solve this unstable issue in the FPFA if you cannot find a solution in the device side, but I need to do some experiments in the next week to confirm what I thought since I need to solve more important issue in another topic during this design. If you would like to close this case, please do it. Again thank so much for your support😊 Thanks, -Fred