Forum Discussion

Occasional Contributor

7 years ago

timing in I/O pads

Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...

KhaiChein_Y_Intel

Regular Contributor

7 years ago

Hi Fred, Here is the Pin-out file: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html Thanks. Best regards, YY

fxu001

Occasional Contributor

7 years ago

Hi YY, How to interpret FF_X149_Y78_N16 for number of 16? How about I have LAB_X149_Y72_N0 convert to FF_X149_Y72_N?? what is tool behavior? Thanks, -Fred

Forum Discussion

timing in I/O pads

Recent Discussions

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

PCIe Root Complex on DK-A5E013BM16AEA

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work