Forum Discussion
fxu001
Occasional Contributor
Occasional Contributortiming in I/O pads
Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi Fred,
Here is the Pin-out file: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
Thanks.
Best regards,
YY
fxu001Occasional Contributor
Occasional ContributorHi YY,
Thank you so much for your information, and I will review it. From Chip editor, I saw the GPIO very close with its pin which it is in the same IOB block, so manually move the cell option is gone. I read your link about Xilinx with Altera comparison paper, and I found there is one option for the compiler setting for three options. Currently I put default, so I would like to try aggressive option. However, I meet memory issue again …
Thanks,
-Fred
