Forum Discussion

fxu001's avatar
fxu001
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

timing in I/O pads

Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Fred,

If you open the Pin Planner (Assignments > Pin Planner), you will see the pins for each bank are colored differently. You may find the region that you want and select the pin, the pin number will appear under pin properties.

Thanks.

Best regards,

YY

fxu001's avatar
fxu001
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Hi YY, I changed GPIO clock to source sync, and data timing reduce from 2.7 to 0.9 for WNS. The TNS also reduce a lot. If we can find a way to turn GPIO data timing, we might solve the issue. DO you have any suggestion? Thanks, -Fred