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fxu001's avatar
fxu001
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

timing in I/O pads

Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Fred,

If you open the Pin Planner (Assignments > Pin Planner), you will see the pins for each bank are colored differently. You may find the region that you want and select the pin, the pin number will appear under pin properties.

Thanks.

Best regards,

YY

fxu001's avatar
fxu001
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Hi YY, I did not answer my question. My question is “do you know the GPIO location close to 3C and 3D I/O pins regions in device 10AX027H4F34I3SG?” The question is to emphasize GPIO cells, I/O regions and device. Could you spend some time to check the device info; then, you will find detail location. Thank you in advance! -Fred