Forum Discussion
fxu001
Occasional Contributor
Occasional Contributortiming in I/O pads
Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi Fred,
If you open the Pin Planner (Assignments > Pin Planner), you will see the pins for each bank are colored differently. You may find the region that you want and select the pin, the pin number will appear under pin properties.
Thanks.
Best regards,
YY
fxu001Hi YY, I did not answer my question. My question is “do you know the GPIO location close to 3C and 3D I/O pins regions in device 10AX027H4F34I3SG?” The question is to emphasize GPIO cells, I/O regions and device. Could you spend some time to check the device info; then, you will find detail location. Thank you in advance! -Fred- fxu001Okay, I give you a little bit simple question. How to find out ALL GPIO location in X-Y coordination?
- fxu001Hi YY, I changed GPIO clock to source sync, and data timing reduce from 2.7 to 0.9 for WNS. The TNS also reduce a lot. If we can find a way to turn GPIO data timing, we might solve the issue. DO you have any suggestion? Thanks, -Fred
