Forum Discussion
fxu001
Occasional Contributor
Occasional Contributortiming in I/O pads
Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi Fred,
It's great to hear that.
You may use
Tools > Chip Planner to analyze and modify the placement of resources.
Assignments > Pin Planner to easily make assignments to device I/O pins within a graphical representation of the target device. The Intel® Quartus® Prime software uses these assignments to place and route your design during device programming.
Assignments > Assignment Editor to view, create, and edit assignments.
Thanks.
Best regards,
YY
fxu001Occasional Contributor
Occasional ContributorHI YY,
Do you know where the GPIO cells close to 3C and 3D I/O pins regions in device 10AX027H4F34I3SG?
Thanks,
-Fred
