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fxu001's avatar
fxu001
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

timing in I/O pads

Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Fred,

It's great to hear that.

You may use

Tools > Chip Planner to analyze and modify the placement of resources.

Assignments > Pin Planner to easily make assignments to device I/O pins within a graphical representation of the target device. The Intel® Quartus® Prime software uses these assignments to place and route your design during device programming.

Assignments > Assignment Editor to view, create, and edit assignments.

Thanks.

Best regards,

YY

  • fxu001's avatar
    fxu001
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago
    Hi YY, Great. Please wait until middle of next week since I will do the experiments about end of week. If anything that I confuse, I will send you an email; otherwise, please close this issue in the middle of next week. Thank you so much for your quick response. Thanks! -Fred
  • fxu001's avatar
    fxu001
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago
    HI YY, Do you know where the GPIO cells close to 3C and 3D I/O pins regions in device 10AX027H4F34I3SG? Thanks, -Fred