Forum Discussion

Occasional Contributor

7 years ago

timing in I/O pads

Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...

KhaiChein_Y_Intel

Regular Contributor

7 years ago

Hi fxu001,

For LOC equivalent assignment , you may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an307.pdf ( Chapter 4.3.2 Table 57)

Thanks.

fxu001

Occasional Contributor

7 years ago

Hi YY, Don’t bother about 8B/10B issue since I found solution from EEtimes which it started K28.5 parameters with RD=-1 and RD=+1 with repeat pattern. Thanks, -Fred

Forum Discussion

timing in I/O pads

Recent Discussions

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

PCIe Root Complex on DK-A5E013BM16AEA

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work