Forum Discussion
fxu001
Occasional Contributor
Occasional Contributortiming in I/O pads
Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi fxu001,
For LOC equivalent assignment , you may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an307.pdf ( Chapter 4.3.2 Table 57)
Thanks.
fxu001Occasional Contributor
Occasional ContributorHi YY,
Great info. Next step is how to open the floorplan editor which it is equivalent Xilinx tool, so I can check the location and lock them; then, I check the timing.
BTW, I solve the timing different in the different I/O banks; basically I evenly distribute AV bus during feed into JESD204B IP. I am close to reach timing in the I/O pads, but I still need to understand Altera tool. Internal timings are okay.
Thanks,
-Fred
