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fxu001's avatar
fxu001
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

timing in I/O pads

Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi fxu001,

Can you provide the design, timing report and sdc for investigation?

Thanks.

fxu001's avatar
fxu001
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Hi YY, If I know how to lock the location floorplan editor, I can alternatively bypass the IO pads timing issue in the system; otherwise, the system will be unstable because timing which I don’t like that scenarios. Thanks, -fred