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Lambert's avatar
Lambert
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

the tx_serial_clock and tx_load_enable signal of one exteral can not drive the lvds_tx in different BANK of Arria V?

Hello everyone, I have one problem is that I need several LVDS pairs for high-speed data output, I only can select the lvds pairs in diffent bank because of layout restrictions. I chose the outp...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello Lambert,

There will be option in PLL to compenstate the phase or you can use the source syn options too.I cant give the definitive number but it is good to try the options

Thank you,

Regards,

Sree

  • Lambert's avatar
    Lambert
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi Sree,

    Thanks for your help.

    Best regards,

    Lambert