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Lambert's avatar
Lambert
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

the tx_serial_clock and tx_load_enable signal of one exteral can not drive the lvds_tx in different BANK of Arria V?

Hello everyone, I have one problem is that I need several LVDS pairs for high-speed data output, I only can select the lvds pairs in diffent bank because of layout restrictions. I chose the outp...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello Lambert,

No problem , I re-created the issue you were seeing. Here is my thought on the same .

i) I am able to FIT differnet bank in the same row (i.e 3A ,4A ,4B,4C & 4D) with PLL.

ii) Quartus wont be able to route PLL between Bank 3A to 7A. from the Archteuture of Arria V A3 device it is clear that it is not possible directly.

One idea ,

We can try to use the PLL cascade and see you able route from 3A bank to 7A . I didn tried as of now .

Attavhed file for your reference for differnet bank in bottom LVDS channel.

Thank you ,

Regards,

Sree

Lambert's avatar
Lambert
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi Sree,

Thanks for your help, I have one problem that if I use the PLL cascade method to provide clock for lvds output locating in 3A and 7A , that means I will need two PLL output clk to drive different lvds output , if so, can I get the better phase relationship between the lvds output locating in 3A bank and the lvds output locating in 7A bank? Because I design this project for 16-bit DAC chip, so the lvds output needs good phase relationgship between each other.

Best regards,

Lambert