the problem about sector and chip earse time of flash S29AL032D?

////////////////////////////////////////////////////////

////////////// Flash State Control ////////////////

always@(posedge iCLK or negedge iRST_n)

begin

if(!iRST_n)

ST<=IDEL;

else

begin

if(mACT) // State Active Flag

begin

if(mStart)

begin

case(r_CMD)

CMD_READ : ST<=READ;

CMD_WRITE : ST<=P1;

CMD_BLK_ERA : ST<=P1;

CMD_SEC_ERA : ST<=P1;

CMD_CHP_ERA : ST<=P1;

CMD_ENTRY_ID: ST<=P1;

CMD_RESET : ST<=RESET;

endcase

end

else

begin

case(ST)

IDEL: ST <= IDEL;

P1: ST <= P2;

P2: begin

case(r_CMD)

CMD_WRITE : ST <= P3_PRG;

CMD_ENTRY_ID: ST <= P3_DEV;

default : ST <= P3;

endcase

end

P3: ST <= P4;

P4: ST <= P5;

P5: begin

case(r_CMD)

CMD_BLK_ERA : ST <= P6_BLK_ERA;

CMD_SEC_ERA : ST <= P6_SEC_ERA;

CMD_CHP_ERA : ST <= P6_CHP_ERA;

endcase

end

P3_PRG: ST <= P4_PRG;

P3_DEV: ST <= IDEL;

P4_PRG: ST <= IDEL;

P6_BLK_ERA: ST <= IDEL;

P6_SEC_ERA: ST <= IDEL;

P6_CHP_ERA: ST <= IDEL;

READ: ST <= IDEL;

RESET: ST <= IDEL;

endcase

end

end

end

end

////////////////////////////////////////////////////////

////////////// Output Finish Control ////////////////

always@(posedge iCLK or negedge iRST_n)

begin

if(!iRST_n)

begin

mFinish<=0;

Cont_Finish<=0;

end

else

begin

if(mACT) // State Active Flag

begin

if(mStart)

begin

mFinish <=1'b0;

Cont_Finish <=0;

end

else

begin

if(Cont_Finish < CMD_Period)

Cont_Finish <= Cont_Finish+1;

else

mFinish <= 1'b1;

end

end

end

end

////////////////////////////////////////////////////////

////////////// Command Period LUT ////////////////////

always@(posedge iCLK)

begin

case(r_CMD)

CMD_READ : CMD_Period <= PER_READ-1;

CMD_WRITE : CMD_Period <= PER_WRITE-1;

CMD_BLK_ERA : CMD_Period <= PER_BLK_ERA-1;

CMD_SEC_ERA : CMD_Period <= PER_SEC_ERA-1;

CMD_CHP_ERA : CMD_Period <= PER_CHP_ERA-1;

CMD_ENTRY_ID: CMD_Period <= PER_ENTRY_ID-1;

CMD_RESET : CMD_Period <= PER_RESET-1;

endcase

end

////////////////////////////////////////////////////////

//////////////// Command State LUT ////////////////

always

begin

case(ST)

IDEL: begin

FL_ADDR <= 22'h000000; mDATA <= 8'h00;

end

P1: begin

FL_ADDR <= 22'h000AAA; mDATA <= 8'hAA;

end

P2: begin

FL_ADDR <= 22'h000555; mDATA <= 8'h55;

end

P3: begin

FL_ADDR <= 22'h000AAA; mDATA <= 8'h80;

end

P4: begin

FL_ADDR <= 22'h000AAA; mDATA <= 8'hAA;

end

P5: begin

FL_ADDR <= 22'h000555; mDATA <= 8'h55;

end

P3_PRG: begin

FL_ADDR <= 22'h000AAA; mDATA <= 8'hA0;

end

P3_DEV: begin

FL_ADDR <= 22'h000AAA; mDATA <= 8'h90;

end

P4_PRG: begin

FL_ADDR <= r_ADDR; mDATA <= r_DATA;

end

P6_BLK_ERA:

begin

FL_ADDR <= r_ADDR<<12; mDATA <= 8'h30;

end

P6_SEC_ERA:

begin

FL_ADDR <= r_ADDR<<16; mDATA <= 8'h50;

end

P6_CHP_ERA:

begin

FL_ADDR <= 22'h000AAA; mDATA <= 8'h10;

end

READ: begin

FL_ADDR <= r_ADDR; mDATA <= 8'h00;

end

RESET: begin

FL_ADDR <= 22'h000000; mDATA <= 8'h00;

end

endcase

end

////////////////////////////////////////////////////////

endmodule