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TGao's avatar
TGao
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

The configuration of FIFO Parameter

Dear Sir/Madam

I will use the IP"Avalon-ST Dual clock FIFO Intel FPGA IP " in Quartus PRO 18.1.

Could you help to check how to config these parameters? I found same hints in datasheet, but don't understand total.

Ted.Gao

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3 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi, I am not able to find the specific information for these parameters and how to configure it.

    Please allow me some time to consult with the internal team.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi, I yet to get an update from the engineering team. Please allow me some time to follow up with them.

    • RichardT_altera's avatar
      RichardT_altera
      Icon for Super Contributor rankSuper Contributor
      5 years ago

      Below are details on how to configure the FIFO Parameter. These will be updated in the future Quartus version.

      Data Width: Width of data going into/out from the FIFO.
      Chanel Width: The width of the channel signal. 0 means that the signal is omitted.
      Use Packets: If enabled, the packet signals will be used. Parameter =1 when enabled, disable = 0
      Prevent Underflow: Enable or disable underflow. Parameter =1 when enabled, disable = 0
      Showahead: When showahead=1, FIFO treats ready ports as read acknowledge that automatically outputs the first valid data word when FIFO is not empty, without asserting the ready signal. When showahead =0, FIFO treats the ready port as read request that only performs read operation and outputs data when the port is asserted.