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I know this is really late, but after spending weeks trying to solve SRAM problems (and finally finding a solution), I want to post in case it's related to your problem.
Newer DE2 boards have SRAM chips ending with "EDBLL" or similar as opposed to the old ones that were just "BLL" or similar (the "ED" is the important part).
These chips are apparently more sensitive to either spikes or reflections on the control lines, which causes random errors throughout memory when writing to the chip.
To solve the problem, I found that someone recommended setting the line terminations to 25 ohm. I found that it actually works better to set the output current strength to 4mA for all control lines (address, WE_N, OE_N, etc.). It solved all my problems.
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Hi there,
First of all, I'd like to thank you on behalf of Terasic for the solution. It will certainly help lots of users who are still struggle with the new SRAM on DE2.
I can see that you mentioned the following two solutions here and the 2nd one actually works better than the 1st one, but I have a question in mind before I summarize the whole thing onto our FAQ section - Do you still need to implement the 1st one on top of the 2nd one or the 2nd one along is more than enough to solve the problem ?
1. setting the line terminations to 25 ohm
2. set the output current strength to 4mA for all control lines (address, WE_N, OE_N, etc.).
Many thanks,
David from Terasic
Honored Contributor
