Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

Yeah, I actually use similar output freqs ("almost" correct since 28.175 clock is not avail on the boards) on my DE2 and DE2-70 and the screen is rock solid on the latter. I have now come to conclusion that there is something going on with the oscillators since the VGA controller clearly has drift on DE2. The PLL generates two clocks for VGA, one for pixel clock and another for OSD framebuffer. These are phase shifted 90 degrees, but for some reason the phase shift and/or pixel/OSD clock seem to jitter (pixels are lit on wrong side of pixel clock or OSD data is not read in on correct phase, take your pick). I need to borrow a scope to see what's going on :-)