Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

This is the original DE2 with EP2C35. I did take a measure at voltages and they seem to be ok, although I can't do any real measurements due to lack of proper scope. What I also now tested was that I changed the VGA PLL to use the 27MHz oscillator as source. I still have jitter, although less than before. So the problem might be elsewhere (some signal termination?). I really hope the FPGA is not faulty.