Terasic DE2-70 Board

Both of you, this attitude is unlikely to get you very far.

Still: download this simple zip with three files: http://thorn.ws/de2-70-flash-leds.zip

This is about the simplest example of a standalone design (it's just flipping bits). I

included the Verilog code below (the indentation is mangled by the altera forum), but you'll need the (trivial) project file and the assignment file from the above zip file. All I did was to take the default example and boil it down.

It really isn't Terasic's job to provide tutorials. That they did anyway to quite impressive.

Regards

Tommy -- (but now I want a DE3!)

module test2(input iCLK_50,

input [17:0] iSW,

output reg [6:0] oHEX0_D, // Seven Segment Digit 0

output reg oHEX0_DP, // Seven Segment Digit 0 decimal point

output reg [6:0] oHEX1_D, // Seven Segment Digit 1

output reg oHEX1_DP, // Seven Segment Digit 1 decimal point

output reg [6:0] oHEX2_D, // Seven Segment Digit 2

output reg oHEX2_DP, // Seven Segment Digit 2 decimal point

output reg [6:0] oHEX3_D, // Seven Segment Digit 3

output reg oHEX3_DP, // Seven Segment Digit 3 decimal point

output reg [6:0] oHEX4_D, // Seven Segment Digit 4

output reg oHEX4_DP, // Seven Segment Digit 4 decimal point

output reg [6:0] oHEX5_D, // Seven Segment Digit 5

output reg oHEX5_DP, // Seven Segment Digit 5 decimal point

output reg [6:0] oHEX6_D, // Seven Segment Digit 6

output reg oHEX6_DP, // Seven Segment Digit 6 decimal point

output reg [6:0] oHEX7_D, // Seven Segment Digit 7

output reg oHEX7_DP, // Seven Segment Digit 7 decimal point

output [17:0] oLEDR);

assign oLEDR = 'h55 ^ iSW;

always @(posedge iCLK_50)

{oHEX5_D,oHEX4_D,oHEX3_D,oHEX2_D,oHEX1_D,oHEX0_D}

<= {oHEX5_D,oHEX4_D,oHEX3_D,oHEX2_D,oHEX1_D,oHEX0_D} + 1;

endmodule