TerASIC DE2-115 GPIO Port question

Am using the DE2_115_web_server application as a baseline...

Am attempting to use a pin (well more than 1, but for discussion's sake we only need to talk about 1) on the GPIO connector as an input to a customer Verilog module. To make the name descriptive to my particular solution, I wanted to rename it from GPIOx to TDR_ROMEN.

Using Quartus Assignment editor, I deleted all of the GPIO references and created the TDR_ROMEN reference. In Pin Planner, I define it as an input on Pin AH_22 (Am using JP5, Pin 33; Used to be GPIO[28])

Next, I created my custom component with an export input tdr_romen. It also contains a Avalon MM Slave. I have instantiated the component in SOPC builder and have validated that I can read/write to registers within the component. The instantiation is called, "statement_coverage_0". If I look at the verilog file for the instantiation, it contains the statement, .tdr_romen (tdr_romen). If I look at the instantiation of the SOPC Builder file, I see the assignment, .tdr_romen_to_the_statement_coverage_0 (tdr_romen_to_the_statement_coverage_0),

Finally, in the top-level DE_115_web_server.v file where the instance of DE2_115_SOPC is instantiated, I added,

.tdr_romen_to_the_statement_coverage_0(TDR_ROMEN)

Am relatively new to FPGA work and so I attempted to trace the flow using the key.v file. My understanding is that TDR_ROMEN references pin AH_22. The value of this pin is passed through the top level file to the instance of DE2_115_SOPC and to the tdr_romen input of my module. In that module, I simply set a register to 0 or 1 based on the value of tdr_romen (done synchronously in an always loop). Pin AH_22 is a hard logic high or low (i.e., it only transitions when I tell it to).

My issue is that I am not seeing a change in the register. I would appreciate if someone could confirm (or rebut) my thought process above.

THanks, in advance,

ME