Honored Contributor
Honored ContributorSorry about that. I think I confused the issue......Sorry for the long winded response as well. I just wanted to say thank you. After a couple of drinks last night, I was able to shift paradigms a little bit. I think the shift will make things more efficient and keep me from asking dumb, esoteric Q's....Many thanks for all of your guidance.
You comments made me wonder if I wasn't executing the tool chain correctly. I went back last night and created a second, different component in Component Builder, integrated it into SOPC Builder and then built the FPGA image in Quartus. I can see the component in the Quartus Project Navigator. So I am assuming that I am executing the tool chain correctly (Please feel free to advise if not). I also see the component# defines show up in the system.h BSP file. The intent of integrating the LED control into StatementCoverage was nothing more than an attempt to debug my VHDL. The SOPC Builder environment accesses the LEDs (and other board peripherals) through a clock_crossing_io component (Base Address 0x09000000). The CPU Data Master connects to the CC IO Slave. The CC IO Master then connects to the peripherals. I added a MM Master in StatementCoverage with the intent to connect to the CC IO MM Slave. Instinct tells me I am OK on the tool chain and a basic understanding of how to build interfaces and connect components. What I believe I'm missing is an understanding of the implementation of any specific component. I also think I am compromising myself as all of the template HDL is written in Verilog and not VHDL (VHDL was legacy suggestion from someone else). I think there are enough .V examples to generate the StatementCoverage component in Verilog. Since I'm an HDL newbie, it won't take me long to shift gears.....
