Honored Contributor
Honored ContributorThanks again for all of the help...
I worked through the SOPC Builder and Avalon documentation. The process seems straight forward enough. I'm sure I'll stumble a few times on the implementation. If I could bother you with an implementation Q (and a bit of background).... We're using the DE2-115 HSMC interface through a custom connector to collect high speed parallel data (Address Bus) on another CPU card (20 year old CPU). I've validated that we receive the HSMC data correctly. I would like to do nothing more than simply set a bit in a memory array for each address that is collected. The CPU address spaces is 0x3ffff. My thought was to create a 0x3ffff by 1 memory element. Once the data has been collected, the Nios would process the data. My first thought was to use the provided DP RAM. However, it looks like the minimum data width is 8 bits. I could use this and shift bits around in the interface VHDL. But, I was wondering if you might provide some design guidance on: 1) Is it possible to create the 0x3ffffx1 array that can be accessed by the nios processor through the avalon interface. 2) Or, is there a better design approach, based on your experience.... Again, apologies for the sophomoric Qs (Still learning) Much appreciated......
