1 ReplyReplies sorted by Most LikedYuanLi_S_IntelRegular Contributor6 years ago是的。可以用给I/O。https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/pcg-01020.pdf （第八页）
YuanLi_S_IntelRegular Contributor6 years ago是的。可以用给I/O。https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/pcg-01020.pdf （第八页）
Recent DiscussionsAgilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_AlteraAgilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPsSyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series designR-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not workPCIe Root Complex on DK-A5E013BM16AEA
New ContributorNew Contributor
YuanLi_S_IntelRegular Contributor
New ContributorRegular Contributor
