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The I2C is not connected to the FPGA. Only through the CPLD.
A google search for MNL-01063-1.3 will result in the rm_svgx_fpga_dev_board.pdf Reference Manual.
Page 15 has the connections. Yes, the JTAG is a Virtual JTAG core.
The FPGA and CPLD are connected using the FSM bus where the FPGA drives a Chip Select into the CPLD.
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Ok, this is pretty much duplicating what is done on a lot of their other boards.
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A service request has been filed... but you how long that can take sometimes. You are correct, if I HAVE to, I can reverse engineer the whole programming sequence...
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Given that they're using a parallel bus with separate address and data, you've got a head-start in that you do not need to decode a multiplexing address/data bus. All you need to figure out is the address map of the MAX V.
Have you looked that the code? Perhaps you'll get lucky and the code was written by a "nice" engineer who wrote the address map in the comments ...
In my experience that is asking a little too much from the code delivered with these kits, but like I said, you might get lucky ... :)
Cheers,
Dave
Honored Contributor
