Stratix V Kit-Programming SiLabs 5338 w/ FPGA

Is the FPGA also connected to the I2C interface to the chips? If it is, then you could create an I2C master in the FPGA.

If not, how is the MAX V connected to the Stratix V?

(Sorry, I don't have this kit installed - post the schematic if you want me to look at it)

File an Altera service request asking for details about the MAX V memory map from the perspective of the Stratix V.

If you're impatient, then create a Modelsim simulation and reverse-engineer the memory map. Since you have the code to the MAX V, you should be able to figure out most things by reading the code, and then create a transaction in the simulation that exercises what you "think" is correct to confirm it.

The JTAG interfaces typically use the SLD Virtual JTAG core, and since you can read the MAX V code, you can tell most of what you need to for accessing the MAX V via that route. However, for your application, you need access from the Stratix V side.

Cheers,

Dave