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Altera_Forum's avatar
Altera_Forum
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13 years ago

Stratix V dev kit programming the clock

I have a customer using our Stratix V development board and they would like to permanently change the default frequency of the programmable oscillator on the board. The Programmable Oscillator included SI570, SI571, and (2x)SI5338.

1. 1. Does the board program the Oscillators through I2C interface after the board power up?

2. 2. If the above (1) case is true, do the default frequency values come from the MAX V CPLD registers?

3. 3. If the above (2) case is true, can customer modify the MAX V CPLD default frequency registers?

4. 4.The Programmable Oscillator device default output frequency is set at the factory, do the development board use those frequency settings after the board power up?

Thanks in advance.

Tim

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    1. Yes.

    2. Yes, from MaxV

    3. Yes, You have access to Max V. however as i understand it: altera will not provide you any modules that can program programable oscillators. so you have to write your own controller for reprogramming oscillators, and you must send the data to them by I2C protocol.

    4. No, if i am correct Max V programs them on board sturtup by it's Flash memory. and fits it to board design. for example Si571 has a range from 10mhz to 1.4ghz. but during board startup it is reprogrammed to operate in range of 10mhz -148.5mhz and later VC pin connecting to the oscillator adjusts it to operate to it's peak (148.5mhz). you can control VC pin of the Si571 to lower the frequency.

    148.5mhz may not necessarily be a peak for stability reasons maybe peak itself is 150mhz but i decided to explain it this way to give you more accurate picture of what is going on in here.

    my information may not be accurate, i don't work at altera so these are all my assumptions based on observations (i have different board but it's similar to yours)

    by they way, if somebody may explain a VCXO oscillator Si571's VC pin control methodology to me i will be vary happy. the FPGA outputs 2 pins "SDI_CLK148_UP" and "SDI_CLK148_DN" which pass some analog circuitry and combine together, then enter into VCXO oscillator Si571's VC pin. as i guess i must send some frequency down to these pins and analog circuitry will develop some static voltage across them which later enters into voltage control (VC) pin but i can't figure it out.