Honored Contributor
Honored ContributorI am little confused as well, the files on Altera/Intel website contains files for revision C, not D, as it marked on the PCB file, however PLX PCIe switch is on the top side and attached to the heatsink through thermoconductive resin, not like shown on the Altera's photo on the kit's Web page. Rev D actual PCB looks quite similar, I thing almost the same, but need to verify carefully. It has test blind-via pads on the bottom sides for most FPGA's ball pins. There is nothing complicated in this board, just be sure that all memory signals, XCVRs, power, and reset are connected the same way and match with errata chip. Otherwise need modify design files to actual wiring and/or apply errata workarounds if possible.
https://alteraforum.com/forum/attachment.php?attachmentid=13851&stc=1 MoSys chip MSR576 (BE1, first generation) for this board is not available anymore. MSR720, MSR820 are current BE2 (Bandwith engine 2) are available on an expansion board for Xilinx Virtex 7 Ultrascale kits. And it's really quite expensive thing ! Altera's design files for Stratix V Adv. Sys. Dev. Kit doesn't have IP for MoSys as well. I found than no any specific designs examples for this kit are available in Altera design store as well. Could easily solder all QDRII+ chips but it's look not actual in case of fat 5SGXEABN chip with enough internal memory cells. Looks like this board is customized for a specific corp. customer. I bought from liquidator warehouse for a really nothing price for such board especially when actually populated GXEABN is about twice expensive than GXEA7 one. Need to get answer from Altera to clear background behind rev. D board. I don't have any specific files for it as well.
