Stratix IV GX Development Kit - QDRII UniPHY Pinning

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Any suggestions?

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I haven't tested the QDRII+, however, I do have the following two options in my Tcl pin assignments script.

#  Clock
if {0} {
    set pin(qdr_top0_k)            {PIN = P23,  IOSTD = "DIFFERENTIAL 1.5-V HSTL CLASS I", SLEW = 3, TERMOUT = "SERIES 50 OHM WITH CALIBRATION"}
    set pin(qdr_top0_k(n))        {PIN = N23}
} else {
    set pin(qdr_top0_k)            {PIN = P23,  IOSTD = "1.5-V HSTL CLASS I", SLEW = 3, TERMOUT = "SERIES 50 OHM WITH CALIBRATION"}
    set pin(qdr_top0_kN)        {PIN = N23,  IOSTD = "1.5-V HSTL CLASS I", SLEW = 3, TERMOUT = "SERIES 50 OHM WITH CALIBRATION"}
}

Try the second option.

The PIN, IOSTD, SLEW, and TERMOUT settings get translated to

IOSTD   {set_instance_assignment -name IO_STANDARD $val -to $port}
PIN     {set_location_assignment -to $port "Pin_$val"}
SLEW    {set_instance_assignment -name SLEW_RATE $val -to $port}
TERMOUT {set_instance_assignment -name OUTPUT_TERMINATION $val -to $port}                

later on in the Tcl script. You can just use the set_instance_assignment versions directly.

Cheers,

Dave