Stratix 4 Developer Board - Topside RAM too many adress input pins

Now I found the solution. On Page 2-51 of the developer boards Reference Manual it says: 'The DDR3 top port consists of a single DDR3 devices, providing 128 Mbyte with a

16-bit data bus. The board supports addressing for up to 4 times the memory if larger devices become available.' So the additional pin is for a bigger device and i can ignore it, because at the moment, it is not connected.