Stratix 10 Transceiver Toolkit User Defined Test Pattern

Hello Ash,

thanks for the answer. It helped me clarified my ideas.

However there is still something that bugs me

I see that in the example design that I am using is included (but not used! it is leave unconnected) this IP core "JTAG to Avalon Master Bridge Intel FPGA IP":

And its signal matches with the ones of the E-Tile Native PHY IP core, as in the Figure 98 that you mentioned: 

Browsing on the online documentation, it looks to me that it is possible to use the "JTAG to Avalon Master Bridge Intel FPGA IP" to send some commands directly from the System Console and interacts with the design.

Let's suppose the I connect correctly this IP to the design (now, as I mentioned, is not connected): would it then be possible to access the transceiver PMA registers and program them from the System Console, instead of writing a custom logic (in VHDL/Verilog) to access these registers?

In other words: would it be possible to execute these instructions just by playing with the System Console?

Would you have maybe some design/examples/tutorials in that case? I see that in this thread the user @SyafieqS_Intel send to another user a zip file containing tutorial related to write and read avalon mm using jtag to avalon master bridge. In case I could have access to that, it could be highly beneficial for my project.

Regards,

Enrico