Forum Discussion

Contributor

7 years ago

Stratix-10 SoC Dev kit- FMC loopback card frequency details

Hi, We are using Stratix-10 SoC Dev kit and we are testing the Transceivers with the help of FMC loopback card received along with the kit. I see there are 2 transceiver clocks connected to REFCLK ...

AR_A_Intel

Super Contributor

7 years ago

Can be found in PCB Schematic. See User Guide on how to determine PCB revision.https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/cyclone-10-gx-development-kit.html

Forum Discussion

Stratix-10 SoC Dev kit- FMC loopback card frequency details

Recent Discussions

Cyclone V GT Dev Kit - new units fail to boot from FPP

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

PCIe Root Complex on DK-A5E013BM16AEA

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs