Stratix 10 SoC Dev Kit - L-tile - FPGA-DDR4 (SODIMM ) Example design

Question

Hi,
I am using stratix 10 SoC dev kit
https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/stratix-10-soc-development-kit.html
I have downloaded the BTS (Board Test System) and checked all the interfaces. But, I see that in the BTS, there is no binary for FPGA-DDR4 (SODIMM, 16GB) interface[BTS has the binary to validate HPS DDR4 memory] .  I tried with example project, but DDR4 SODIMM Calibration done is not observed. 
Can anyone share the exact project to validate the  FPGA-DDR4 (SODIMM, 16GB)  interface.
With Regards,
HPB

ybin · Answer

Hello,
Normally, there is one UDIMM memory in Stratix10 Devkit, not SODIMM. You mean that you just got SODIMM, not UDIMM, is that right? BTW, where do got the Devkit, from Intel side or agent?

hbhat2 · Answer

Hi,
As per stratix 10 SoC product page (below link) &amp; user guide, it is mentioned as SODIMM (attached the snapsot)
https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/stratix-10-soc-development-kit.html

We got it from Intel's authorized distribution channel here in India (Cytech).

With Regards,
HPB

hbhat2 · Answer

Hi,
Anybody has the FPGA-DDR4 (16GB) design for Stratix 10 SoC dev kit?
With regards,
HPB

ybin · Answer

Hi,
You need to download package installer from below page, and then you can find the design locates in download zip file. It locates in examples/sodimm_ddr4 folder.
https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/stratix-10-soc-development-kit.html

hbhat2 · Answer

Hi,
Yes, I have downloaded the package &amp; tried to create the project as mentioned in the readme file.
I ran the below command in command prompt &amp; I am getting the error message while creating the project
quartus_sh -t make_qii_design.tcl
------------------------------------------------------------------------------------------------
Error (23035): Tcl error: child process exited abnormallywhile executing"exec -ignorestderr $qsys_generate_exe_path $qsys_file --pro --synthesis --family=$family --part=$device &gt;&gt;&amp; ip_generate.out"(file "make_qii_design.tcl" line 98)------------------------------------------------child process exited abnormallywhile executing"exec -ignorestderr $qsys_generate_exe_path $qsys_file --pro --synthesis --family=$family --part=$device &gt;&gt;&amp; ip_generate.out"(file "make_qii_design.tcl" line 98)------------------------------------------------Error (23031): Evaluation of Tcl script make_qii_design.tcl unsuccessfulError: Quartus Prime Shell was unsuccessful. 2 errors, 0 warningsError: Peak virtual memory: 4871 megabytesError: Processing ended: Tue Aug 25 09:59:37 2020Error: Elapsed time: 00:00:23
------------------------------------------------------------------------------------------
I am using Quartus pro 18.1 &amp; licensed for stratix 10 device.
With regards,
HPB

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Stratix 10 SoC Dev Kit - L-tile - FPGA-DDR4 (SODIMM ) Example design

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