Stratix 10 SoC Dev Kit - L-tile - FPGA-DDR4 (SODIMM ) Example design

Hi,

I am using stratix 10 SoC dev kit

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/stratix-10-soc-development-kit.html

I have downloaded the BTS (Board Test System) and checked all the interfaces. But, I see that in the BTS, there is no binary for FPGA-DDR4 (SODIMM, 16GB) interface[BTS has the binary to validate HPS DDR4 memory] . I tried with example project, but DDR4 SODIMM Calibration done is not observed.

Can anyone share the exact project to validate the FPGA-DDR4 (SODIMM, 16GB) interface.

With Regards,

HPB