Stratix 10 Devkit Board Update Portal

Hello,

I apologize for my slow response.

1) This is Quartus via the VNC so I'm not sure if I should touch the .dat file

2) OS:

NAME="SLES"
VERSION="12-SP5"
VERSION_ID="12.5"
PRETTY_NAME="SUSE Linux Enterprise Server 12 SP5"

3) Attached

4) Attached

Also, I did want to mention that I did manage to create the binary file through other means... but it caused the board to stop operating entirely. I needed to do this because this Stratix 10 FPGA is unable to produce .pof files through quartus natively. Essentially we needed to factory restore the board after all of this though.

Steps to get files required for board update portal:

1. Open Quartus

2. Assignments -> Device -> Device and pin options -> Device and pin options -> Configuration -> Set Configuration Scheme to AVSTx32

3. Recompile

4. File -> Programming File Generator

• Set Configuration mode to AVST x32
• Under output files, check Programmer Object File (.pof)
• Under input files, specify the .sof file
• Under Configuration Device, add device CFI_1GB (unsure if this was correct)

5. Generate the .pof

6. Ran the "build_hw.sh" to produce the .bin file

7. Ran the following the produce the .flash file for nios

• elf2flash --base=0x0 --end=0x0FFFFFFF --reset=0x09140000 --input=yourfile_sw.elf --output=yourfile_sw.flash

8. Put these files into the board update portal

Thank you

Hi there. I can't get the board update portal to work properly.

1. For the stratix 10 transceiver signal integrity devkit, quartus can't inherently create the correct kind of "bin" file so I needed to try and create the file using "file -> convert programming files"

2. When I programmed the flash using the board update portal, the board became inoperable and I needed to figure out how to factory reset it.

The rest of the supplemental information can be found in my previous posts.

Thank you.

Hello,

I've already tried that and it doesn't work. The error is in the first part of this post.

My response on "‎09-06-2022" details what exactly I did to get around the errors.

Thanks,

Nick

Hi Kelly,

Even though I navigated around the errors... nothing works. When I followed those steps the on-board CPLD MAX V flash was completely erased and the board had to be factory restored.

In other words, nothing works. Please read my previous messages on this post; there has been no progress with respect to the board update portal. I navigate through the errors but the end result is broken.

Nick

Hello,

I apologize for my lack of response; I've been tasked with other things and this was put on the backburner due to priority.

The script can be found here: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-gx-signal-integrity.html for the "Intel® Stratix® 10 GX SI H-Tile Package". This script was gathered from Intel's supplied files for the stratix 10 GX signal integrity development kit.

Is there a more-updated script that I can use that utilizes "quartus_pfg "?

What is the different between "quartus_cpf " and "quartus_pfg "?

Thanks,

Nick