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asorouri's avatar
asorouri
Icon for New Contributor rankNew Contributor
7 months ago

Stratix 10 DDR4 timing model & package model

Hi I am running board level DDR4 simulation with a Stratix 10 SoC and a Mercury 4N1G72T-24B3I SDRAM device. I need timing model and package model for this SoC. I prefer a s-parameter package model i...
Fpga Devkit
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
7 months ago

Hi Ali,


I believe the tool that you mentioned is Quartus software.

The Quartus has the IBIS Writer that can be used to generate the IBIS model.

It's can generate the model based on the design that you have in Quartus.

You can refer to this link to generate a custom IBIS model.

Link: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#eda/boardlevel/ibis/eda_pro_ibis_out.htm?erpm_id=10673258_ts1747729761093#eda/boardlevel/ibis/eda_pro_ibis_out.htm


This IBIS model is representing the FPGA side. For memory side, usually we use the vendor provided IBIS model. You may use JEDEC standard model in this simulation.


Regards,

Adzim