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New ContributorStratix 10 1G/2.5G Ethernet reconfiguration not working in hardware
Hi dlim,
I finally managed to communicate with the PHY.
One problem was that some of the switches were not in the right position, so the pointer in the scripts was not pointing to the S10 FPGA.
Also a reset_n on the fw side was not negated (and so it was always in resetting all the time).
This is then solved.
A part for one register (for auto negotiation enabling) that I can't write.
But I would open a new ticket for that.
Thanks for your support.
Alessandra
New ContributorHi,
I have been testing a bit more.
In simulation, injecting the avalon MM commands directly after the JTAG bridge to e.g. change the configuration of the PHY works well. So it's not a problem of the address mapping block.
To make sure that the read/write commands are actually propagated in hw, I added some counters on the read/write signal (simulation is ok).
BUT when I move to hardware and I launch the commands from the console, nothing is exiting the JTAG bridge. No counter is increasing, they all stay at zero.
It looks like, either the scripts or the Bridge is having an issue.
I am no sure on how to proceed with the debug. Let me know if you have suggestions.
Best regards,
Alessandra
Ps. more info on how I am using the console.
(i) Opening Quartus, (ii) uploading the firmware, (iii) opening the debug console.
I cd to the folder were the scripts are and after sourcing the main.tcl I am writing:
- reg_write 0x000000 0x0 0
- reg_write 0x000000 0x4 [expr ((1 << 16) | (0 << 0))]
that are the very same commands written in the rcfg/mge_rcfg_inc.tcl file (always from the example project) simply with the numbers explicitly written. (My MGE reconfig module has base address 0x00000000, like in the example project.)
And these correspond as well to the avalon mm commands that in simulation work.
New ContributorSome more information:
Trought the get_service_paths master I discovered that the script was pointing to the wrong object on the jtag chain. It was set to 0, but now it's set to 1 (the stratix 10 MX on the devkit)
% get_service_paths master
{/devices/10M16S(A|C)@2#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master} {/devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master} {/devices/VTAP10@3#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master}
Still, I have no success as the requests timeout.
% set port_id [lindex [get_service_paths master] 1]
/devices/1SM21BHN(1|2|3)|1SM21BHU1|..@1#USB-1#Intel Stratix 10 MX FPGA Development Kit/(link)/JTAG/(110:132 v1 #0)/phy_0/master
% open_service master $port_id
% master_read_32 $port_id 0x50000000 1
error: master_read_32: This transaction did not complete in 60 seconds. System Console is giving up.
while executing
"master_read_32 $port_id 0x50000000 1"
And no signals are propagated after the JTAG bridge.. could it be that the development kit of the S10 MX needs to be setup somehow?
