Forum Discussion
hsyn
New Contributor
New ContributorSPI TIMING CONSTRAINTS
Hello,
How can I constraint spi signals shows on below?
I didn't understand how I can write a sdc file for this scenario.
KennyT_altera
Super Contributor
Super ContributorHi, you may refer to https://community.intel.com/t5/FPGA-Wiki/Constrain-SPI-Core/ta-p/735358
It had example datasheet over there. You can take a look and follow.
