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Altera_Forum
Honored Contributor
11 years agoSockit VIP demonstration
I use like template the Sockit VIP demonstration, I only use the HPS, DDR3 memory in FPGA side, a Frame Reader and a Clocked Video Oputput . I removed all the rest of video IP cores. Previous to run ...
Altera_Forum
Honored Contributor
11 years agoThank you,
Screen shots of the system in the attached .zip file. Most relevant details in the system: -mem_ddr3.afi_clock is 150Mhz and it is connected to h2f axi.clock and to the clock_master in the frame reader. -pll has 2 outputs: 65 Mhz to the clock_bridge (used for the VGA out) and 130 Mhz to the frame_reader:clock_reset input, and to the clocked_video_output:is_clk_rst -the Avalon mm-slave is connected to the h2f_axi_master in the HPS and to the Avalon_master in the frame_reader If I use a test pattern generator, the color bars are generated, but with the frame buffer, there is nothing in the screen. Maybe the problem is my C code: According to the sample C code, the configuration for the frame reader ip are: to declare the frame reader as static volatile pointer: static volatile unsigned long *h2p_vip_frame_reader0_addr=NULL; then pass the register values directly like this: h2p_vip_frame_reader0_addr[0]=0x0; h2p_vip_frame_reader0_addr[4]=DEMO_VGA_FRAME0_ADDR+FR0_FRAME0_OFFSET; h2p_vip_frame_reader0_addr[5]=word; h2p_vip_frame_reader0_addr[6]=cycle; h2p_vip_frame_reader0_addr[8]=Width; h2p_vip_frame_reader0_addr[9]=Height; h2p_vip_frame_reader0_addr[10]=interlace; h2p_vip_frame_reader0_addr[0]=0x1; h2p_vip_frame_reader0_addr[3]=0; Like other examples and codes, the values of the registers are this way: *h2p_vip_frame_reader0_addr=SOME VALUE; Setting the value at indirect way. So, I don't understand if my guess is wrong, but I think the first way shouldn't work. Anyway, I tried both ways and still doesn't works. What should be the right way?