Honored ContributorDoes anyone have a working example that uses the hard DDR3 controller to access memory from the FPGA? There are two examples (with and without qsys) of using DDR3 without the hard controller, but none that use it. Is there something wrong with the hard DDR3 controller? i'd think you would want to use it because it is faster and doesn't consume as many FPGA resources.
Thanks.
Honored ContributorHi, I was hunting for a similar example some time back, and found an example for cyclone v gt here:
https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html Download the kit installation, and after that search for "q_sys_hmc.qsys" in the examples folderHonored ContributorThanks for the information. I ended up copying the terasic example that uses a soft memory controller for that project. I'll take a look at it and see if it's possible to port it to my sockit board.
