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WabG's avatar
WabG
Icon for New Contributor rankNew Contributor
1 year ago

SoC Cyclone V : FPGA full configuration from HPS FPGA Manager, MSEL issue ?

Dear support, We are using a SoC cyclone V and want to configure the FPGA portion from HPS through the FPGA manager. We have followed the procedure described in HPS Technical Reference Manual (cv_5...
Board Debug
Fpga Devkit
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi WabG,

To configure the FPGA, you will need to perform 'bridge enable' cmd in Uboot.

Try to run bridge enable then only configure/load the FPGA bitstream.

Thanks.

Regards,

Aik Eu

  • WabG's avatar
    WabG
    Icon for New Contributor rankNew Contributor
    1 year ago

    Aik Eu,

    Even with the bridge enable command, the FPGA isn't configured under U-Boot.

    But, with a good MSEL setting, the FPGA load is successful.

    Do you confirm, it is possible to use the FPGA manager to load the FPGA portion even with a wrong MSEL setting ?

    How the bit enable of control register of FPGA Manager should be interpreted ?

    En bit = 1 : "FPGA Manager drives configuration inputs to the CB. Used when HPS configures the FPGA."

    My interpretation was "FPGA manager" bypasses the MSEL setting when the bit is set to 1.

    Regards,

    WabG