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Altera_Forum
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15 years ago

SIV PCIe high performance ref design data can arrive out of order

Hi, We've been using the Stratix IV PCIe high-performance reference design for a while and see some funny behavior when performing a read DMA: the data arrives into our logic out of order inte...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi Nodec,

No we still haven't got to the bottom of this and are still investigating. We have noticed that we don't see the re-ordering occuring on a Xeon/X58-based platform, but do see it on an nVidia GeForce 9300-ITX MCP7A-based Zotac platform. We haven't been able to get any details on the MCP7A chipset to see how it deals with relaxed ordering - note we set the relaxed ordering bit in the read_request headers to do strict ordering, rather than relaxed ordering. Maybe nVidia assumes it can do relaxed ordering to maximise throughput as they assume the PCIe is being used to transfer graphics data?!

So our current workaround is to use a Xeon/X58 platform but it also has thrown up a problem where we see extraneous writes to our EP memory map every 13ms, which gradually corrupts our whole memory map over time - we're using signaltap today to work out what type of packets are coming across from RC to EP to cause this.

Cheers,

Dwayne