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Savino's avatar
Savino
Icon for New Contributor rankNew Contributor
10 months ago
Solved

Simulating by ModelSIM signals multiple blocks nested inside each other on quartus||

good morning, in the quartus|| environment I inserted in a new schematic file, two blocks: an LPM Counter and an LPM compare and other signal like clock, ect. After that I created a new block contain...
Fpga Devkit
  • ShengN_altera's avatar
    ShengN_altera
    10 months ago

    Hi,

    Please follow the previous mentioned steps.

    In work library, double click the main screenshot:

    In object panel, you'll see those signals clk, clk_en, cnt_en, as_res, spi, out. Select all and right-click -> Add Wave screenshot:

    Those signals will be added to wave panel screenshot:

    Thanks,

    Regards,

    Sheng

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
10 months ago

Hi,

In Project Navigator -> Files, all the .bdf need to be changed to HDL. Double click the .bdf -> File -> Create/Update -> Create HDL Design File from Current File.

Then include the HDL files (.v/.vhd) to Project Navigator and remove the .bdf from Project Navigator. Attached the design for your reference.

Thanks,

Regards,

Sheng