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Savino's avatar
Savino
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1 year ago
Solved

Simulating by ModelSIM signals multiple blocks nested inside each other on quartus||

good morning, in the quartus|| environment I inserted in a new schematic file, two blocks: an LPM Counter and an LPM compare and other signal like clock, ect. After that I created a new block contain...
Fpga Devkit
  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi,

    Please follow the previous mentioned steps.

    In work library, double click the main screenshot:

    In object panel, you'll see those signals clk, clk_en, cnt_en, as_res, spi, out. Select all and right-click -> Add Wave screenshot:

    Those signals will be added to wave panel screenshot:

    Thanks,

    Regards,

    Sheng

Savino's avatar
Savino
Icon for New Contributor rankNew Contributor
1 year ago

hi, i am a little bit confused. in order to simulate all the signals I need, do I have to convert the main file (which contains other blocks) into an HDL file? How do I do it?

  • Savino's avatar
    Savino
    Icon for New Contributor rankNew Contributor
    1 year ago

    I converted the file in verilog HDL but when i lunch modelSIM, in work folder still i dont see all the entire signal i need