Forum Discussion

Savino's avatar
Savino
Icon for New Contributor rankNew Contributor
10 months ago
Solved

Simulating by ModelSIM on quartus|| 9.0 - XOR function bus_signals error in verilog file

Good evening everyone, for several hours I have been running into a problem using quartus|| 9.0 and ModelSim. I have created a very simple project with a bus input and a bus output, and an XOR funct...
Fpga Devkit
  • ShengN_altera's avatar
    ShengN_altera
    10 months ago

    Hi Savino,


    I misunderstood the situation. As mentioned by sstrell, the input must be same width. Using same width will be no problem.

    You're using different width, that's why causing the bug.


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
10 months ago

Hi,


Please change this assign out = in[29:0] ^ {in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in}[30]; to this assign out = in[29:0] ^ in[30];


Thanks,

Regards,

Sheng