Simulating by ModelSIM on quartus|| 9.0 - XOR function bus_signals error in verilog file

Good evening everyone, for several hours I have been running into a problem using quartus|| 9.0 and ModelSim.

I have created a very simple project with a bus input and a bus output, and an XOR function inside. The program synthesis is successful and so is the simulation. Unfortunately, as soon as I try to simulate the program via ModelSIM an error appears. Basically:
- given the program written and compiled with a .bdf file
- I create the .hdl file (so I delete the .bdf file)
- as soon as I launch the RTL simulation, a syntax error appears in the file automatically created by quartus|| as follows:
assign out = in[29:0] ^ {in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in}[30];
if I try to perform the XOR operation between non-bus data (single data) I have no error. It seems that the XOR function between multiple data such as data buses generates this error. Is there a solution?
I attach the project.