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Savino's avatar
Savino
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Simulating by ModelSIM on quartus|| 9.0 - XOR function bus_signals error in verilog file

Good evening everyone, for several hours I have been running into a problem using quartus|| 9.0 and ModelSim. I have created a very simple project with a bus input and a bus output, and an XOR funct...
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  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi Savino,


    I misunderstood the situation. As mentioned by sstrell, the input must be same width. Using same width will be no problem.

    You're using different width, that's why causing the bug.


    Thanks,

    Regards,

    Sheng


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

An XOR between a bus and a single signal makes no sense. The bus widths must match to perform a bit-by-bit XOR operation.