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binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Signaltap waiting for clock on PCIe example design

Hi there, I am running PCIe example design on AGF027 development kit. I am running Gen4, 1x16 Endpoint reference design. Using Signal tap to check basic functionality. I ran through the process as m...
Fpga Devkit
  • binupr's avatar
    binupr
    1 year ago

    Hi Wincent,

    Finally narrowed down the issue.

    Issue was that the Switch selection option for PCIe reference clock mentioned in Intel/Altera AGF027 dev kit user guide was incorrect and this led to the clock buffer put in wrong input mode.

    Below is screenshot from User Guide.

    Switch 4.3 should be set to OFF to receive local clock. As you can see the documentation suggests setting to be ON to receive local clock.

    Could you please feed this back to the corresponding documentation team within Intel/Altera to get this updated?

    Thanks

    Binu

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Binu


As the solution is found, I will proceed to close this thread

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences.

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.