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anaza3's avatar
anaza3
Icon for New Contributor rankNew Contributor
7 years ago

Sharing SDRAM by two NIOS cores

Hi, I am working on DE0-CV board. I am trying to share SDRAM by two NIOS cores. They don't need to share data, basically they just need to partition the SDRAM and run two different applications th...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

HI,

DE0 board only contains 1 SDRAM memory device interface. Therefore, you can't create 2 SDRAM IP in QSYS.

It would be easier to hook up everything under same QSYS interface rather than create sub-block design (core1, core2) to verify the design connection first. It's easier to manage to QSYS addressing as well.

For instance, using core1 sub-block design. I tried out following combination

  • 1 NIOS to connect to both on chip RAM and SDRAM (ok, no error)
  • 2 NIOS to connect to same on chip RAM (ok, no error)

You can read more about QSYS usage guideline in below link as well

Thanks.

Regards,

dlim