Sharing SDRAM by two NIOS cores

HI,

DE0 board only contains 1 SDRAM memory device interface. Therefore, you can't create 2 SDRAM IP in QSYS.

It would be easier to hook up everything under same QSYS interface rather than create sub-block design (core1, core2) to verify the design connection first. It's easier to manage to QSYS addressing as well.

For instance, using core1 sub-block design. I tried out following combination

• 1 NIOS to connect to both on chip RAM and SDRAM (ok, no error)
• 2 NIOS to connect to same on chip RAM (ok, no error)

You can read more about QSYS usage guideline in below link as well

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer.pdf

Thanks.

Regards,

dlim