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ABADY1000's avatar
ABADY1000
Icon for New Contributor rankNew Contributor
3 years ago

Setting True LVDS input and output in MAX10

I am creating a new board based on MAX10 FPGA, so I started Pin Planning Project. As read in MAX10 docs, bank 3 and 4 support True LVDS output, but when I try to set LVDS protocol to the pins in b...
AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,

There are requirement to do that and you have to follow the right specification (like example the right I/O standard) to be able to do that. Please refer our to our document (Intel® MAX® 10 FPGA Device Datasheet) on your design.

Thank you

ABADY1000's avatar
ABADY1000
Icon for New Contributor rankNew Contributor
3 years ago

Hello AminT_Intel,

Mr. AminT_Intel, the device supports True LVDS as stated in (Intel® MAX® 10 FPGA Device Datasheet), so why I can't use LVDS in these bank3 and 4 pins ?!

Please if are willing to help me, give me a good answer, not a general statement.

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,

    True LVDS input buffer is supported in all I/O banks

    True LVDS output buffer is only supported on bottom I/O banks.

    Please refer to Intel® MAX® 10 High-Speed LVDS I/O User Guide for detailed explanation.

    Thank you.

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.