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GTown's avatar
GTown
Icon for New Contributor rankNew Contributor
6 years ago

Setting 100 MHz on Stratix IV GX

I have a working design using the usual 50MHz clock which I've had running successfully on a much smaller FPGA from Xlinix at 100 MHz. I've googled and scoured the forum, but can't quite find a solution. One post that came close involved schematic and block diagrams, but all my source is in Verilog. I've tried simply selecting a different clock source, but all the alternatives appear to be "differential clocks" as opposed to single-ended and won't compile. I would actually like to test my design at much higher clock rates than just 100 MHz to see if the logic will keep up and although it would be nice to have Quartus II simulate and test that for me, I'd also like to just be able to try it and see. So here's what I'm looking for:

i) What do I need to do (hopefully in verilog since that's my only source) to try a higher clock speed

ii) How do I get around this "differential clock output" problem

iii) How do I tell Quartus II that the signal in question is a clock. I noticed when it compiled it squawked about "no clock" but then later in the compile noticed that my signal called "clk" was connected to pin AC34 which it knew was a clock and it said something about "promoting" my clk to a "clock".

Thanks for any help.

-gt-

2 Replies

  • Abe's avatar
    Abe
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hi,

    When using designs with clocks in them, you have two steps involved:

    1. Assign the clock to respective clock pin via Pin Planner / Assignment editor. If the clock is a single-ended one , you can connect it to any of the CLKn/CLKp pins on the device.
    2. Add a SDC (Synopsys Design Constraints) file to the project which will mention the clocks , delays, etc. In the SDC you will mention the clock period aka Frequency of operation and have the tool look for the associated clock in the design and apply to it.
    3. Also mention the input and output delays, false-paths and multi-cycle paths if any.

    all of these put together will ensure that your design works as it should for that required frequency/timing requirements.

    Examples of SDC file: 

    #**************************************************************
# Time Information
#**************************************************************
 
set_time_format -unit ns -decimal_places 3
 
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_Clk_50Mhz}]
create_clock -name {vClk} -period 20.000 -waveform { 0.000 10.000 } 
 
#**************************************************************
# Clock Uncertainity
#**************************************************************
derive_clock_uncertainty
 
#**************************************************************
# Input Delay
#**************************************************************
set_input_delay -clock { vClk } 0.0 [get_ports {FPGA_Clk_50Mhz FPGA_reset}]
set_input_delay -clock { vClk } 0.0 [get_ports {altera_reserved_tck altera_reserved_tdi altera_reserved_tms}]
 
 
#**************************************************************
# Output Delay
#**************************************************************
set_output_delay -clock { vClk } 0.0 [get_ports timer_out]
set_output_delay -clock { vClk } 0.0 [get_ports altera_reserved_tdo]
  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago
    Hi, Kindly find the inline answers. What do I need to do (hopefully in verilog since that's my only source) to try a higher clock speed >> Can get lot of codes from the google . Appending a simple program module frequency_divider_by2 ( clk ,rst,out_clk ); output reg out_clk; input clk ; input rst; always @(posedge clk) begin if (~rst) out_clk <= 1'b0; else out_clk <= ~out_clk; end endmodule ii) How do I get around this "differential clock output" problem In Quartus ,Open the pin planner change the I/O standard to LVDS iii) How do I tell Quartus II that the signal in question is a clock. I noticed when it compiled it squawked about "no clock" but then later in the compile noticed that my signal called "clk" was connected to pin AC34 which it knew was a clock and it said something about "promoting" my clk to a "clock". >> Connect to the specific dedicated clock pins . Hope it clarifies